In a liquid crystal display (LCD), a layer of liquid crystal material is sandwiched between two electrodes (both of which, in the case of a transmissive liquid crystal display, are transparent). In operation first and second voltages are applied respectively to the electrodes, and the state of the liquid crystal material is dictated by the absolute value of the difference between the first voltage and the second voltage. The state of the liquid crystal material controls how much light is passed through the liquid crystal display, and thus the brightness.
A liquid crystal display generally comprises a polarity of independently addressable picture elements or “pixels”. In an active matrix LCD, one electrode is usually common to all pixels (the “common electrode” or “counter electrode”), while the other electrode is patterned to define a polarity of independently addressable electrodes, each of which corresponds to a pixel (the “pixel electrodes”). A simplified diagram of a pixel is shown in FIG. 1. VCOM represents the voltage applied to the counter electrode 1 of the pixel, while the source line SL, gate line GL and pixel transistor 3 control the voltage applied to the pixel electrode 2 of the pixel. In brief, suitable drive voltages are applied to the source line SL by a display driver DD and to the gate line GL by a suitable drive circuit (not shown in FIG. 1). A suitable voltage to switch the pixel transistor ON is applied to the gate line GL, which is connected to the gate of the pixel transistor. While the pixel transistor 3 is switched ON the pixel electrode is connected to the source line SL and the pixel may be addressed by applying a suitable voltage to the source line.
To prevent long-term degradation of the liquid crystal material in a display, the liquid crystal material must be driven to alternating positive and negative voltages each time it is refreshed (which occurs generally 50-60 times per second), such that the time-averaged dc voltage across the liquid crystal material is zero.
Consider a normally white LCD, where                The “white voltage” (the voltage that must be applied across the liquid crystal material to give 100% transmission of light), VW=1V        The “black voltage” (the voltage that must be applied across the liquid crystal material to give 0% transmission of light), VB=3V        
In this example, it is possible to achieve an alternating voltage across the liquid crystal material in one of two ways:                The counter electrode voltage VCOM can be fixed, and the voltage VPIXEL applied to the pixel electrode can be driven alternately to values above and below the fixed value (see FIG. 2(a)). For example, if the counter electrode voltage VCOM is fixed at 2V, the pixel voltage may be alternately in the range 3 to 5V and the range 1 to −1V.        The range for the pixel voltage can be chosen to cover the range of required LC voltages (VB−VW=2V), and counter electrode voltage VCOM can alternate to give the correct dc level to the liquid crystal (see FIG. 2(b)). For example, the pixel voltage VPIXEL may always be in the range 0 to 2V, and the counter electrode voltage VCOM may alternate between −1V and 3V.        
It can be seen that use of an alternating counter electrode voltage VCOM reduces the range of voltages required to be supplied to the pixel electrode 2, and therefore simplifies the design of the digital/analogue converters (DACs) which generate these voltages. In typical systems, the counter electrode voltage VCOM alternates every row time (approximately every 50 μs).
However, use of an alternating counter electrode voltage VCOM also has disadvantages:                The counter electrode 1 presents a large capacitance, which therefore takes time to charge. During this time, data cannot be written to the pixels, so the time between rows (blanking time) is increased.        The counter electrode 1 is a large area of conductor, which is therefore susceptible to electro-static discharge (ESD). The usual solution to ESD is to provide a low-resistance path to ground via a protection diode at the point where connection is made to the glass of the display, but such circuits usually contain resistors and so are generally omitted for the counter electrode (so that it charges as quickly as possible). As a result, the counter electrode provides a conduction path into the VCOM driver circuit, which may be damaged by ESD.        Since the load on counter electrode voltage VCOM is large, it is often driven by a very large op-amp buffer, which consumes a large quiescent current. However, since the counter electrode voltage VCOM is switched infrequently, only a small proportion of this current is used to drive the load, with the remainder flowing to ground through the buffer, consuming unnecessary power.        
In general, it is preferable to minimise the number of voltage references required in a system. Each reference must be accurately generated, and then buffered (if it will supply current).
To reduce system complexity, it would be preferable for:                the DACs that supply the pixel voltage to use as the reference voltages the same voltages as provided by the supply rails for, for example, logic circuits and clock circuits in the DAC (or other circuits in the system);        the counter electrode voltage VCOM to be fixed, ideally to ground (to overcome the problem ESD);        or (if VCOM cannot be fixed) the difference between the high and low values of counter electrode voltage VCOM to be the same as the voltage of one supply rail. For example, in a system with supply rails of 0V, 3V and 5V, the difference between the high and low values of VCOM would ideally be 3V or 5V. In this case, the counter electrode voltage VCOM could be driven by an inverter, which consumes less quiescent current than an op-amp buffer.        
Note that it is possible to generate an adjustable dc offset for VCOM more easily, since this reference is not required to supply current.
FIG. 3 of the accompanying drawings illustrates a known type of switched capacitor digital/analogue converter (DAC) for converting an n-bit digital word (or n-bit digital “code”) to a corresponding analogue output. The DAC comprises n-capacitors C1, . . . , Cn. The DAC further comprises a terminating capacitor CTERM connected between the input of a unity gain buffer 4 and ground. The first electrodes of the capacitors C1, . . . , Cn are connected together and to the first terminal of the terminating capacitor CTERM. The second terminal of each of the capacitors C1, . . . , Cn is connected to a respective switch, such as 5, which selectively connects the second electrode to a first or second reference voltage input V1 or V2 in accordance with the state or value of a corresponding bit of the digital word. The output of the buffer 4 drives a capacitive load CLOAD, for example in the form of a data line or column electrode of an active matrix of a liquid crystal device.
The DAC has two phases of operation, namely a resetting or “zeroing” phase and a converting or “decoding” phase, controlled by timing signals which are not illustrated in FIG. 3. During the zeroing phase, the first and second electrodes of the capacitors C1, . . . , Cn and the first electrode of the terminating capacitor CTERM are connected together by an electronic switch 6 and to the first reference voltage input V1. The capacitors C1, . . . , Cn are therefore discharged so that the total charge stored in the DAC is equal to V1CTERM.
During the decoding phase, the second electrode of each capacitor Ci is connected to the first reference voltage input V1 or to the second reference voltage input V2 according to the value of the ith bit of the digital input word. The charge stored in the DAC is given by:
                    Q        =                                            ∑              i                        ⁢                                          b                i                            ⁢                                                C                  i                                ⁡                                  (                                                            V                      DAC                                        -                                          V                      2                                                        )                                                              +                                    ∑              i                        ⁢                                          (                                  1                  -                                      b                    i                                                  )                            ⁢                                                C                  i                                ⁡                                  (                                                            V                      DAC                                        -                                          V                      1                                                        )                                                              +                                    V              DAC                        ⁢                          C              TERM                                                          (        1        )            
where bi is the ith bit of the input digital word and VDAC is the voltage at the first electrodes of the capacitors C1, . . . , Cn and CTERM. The output voltage is therefore given by:
                              V          DAC                =                              V            OUT                    =                                                                                          ∑                    i                                    ⁢                                                            b                      i                                        ⁢                                          C                      i                                                                                                                                  ∑                      i                                        ⁢                                          C                      i                                                        +                                      C                    TERM                                                              ⁢                              (                                                      V                    2                                    -                                      V                    1                                                  )                                      +                          V              1                                                          (        2        )            
In general, Ci=2(i-1) C1 and C1=CTERM. This results in a set of output voltages which are linearly related to the input digital word.
In order to isolate the load capacitance from the DAC and to prevent it from affecting the conversion process, the unity gain buffer 4 is provided. However, such buffers are a substantial source of power consumption, and it is therefore desirable to omit the buffer 4 in a low power system. In this case, the load capacitance replaces CTERM, as shown in FIG. 4.
UK patent application No. 0500537.6 discloses a DAC suitable for use without a buffer amplifier. This DAC is shown in FIG. 5.
The components of an n-bit DAC of UK patent application No. 0500537.6 are an (n−1)-bit switched capacitor DAC of the type described in FIG. 3 and three reference voltage sources, V1, V2, V3. One of the reference voltage sources (V1) is connected to the top plate of the capacitor array during the zeroing phase as switch 7 is closed by a timing signal F1. The other reference voltage sources (V2, V3) are connected to the bottom plates of the capacitors Ci according to the input data and timing signals F1, F2, by means of respective switches 8.
In the preferred embodiment, the voltages on the bottom plates are configured so that the capacitors can inject charge onto the DAC output in either a positive or negative sense. In this way, the output of the DAC covers a range of voltages symmetrically above and below the first reference voltage, as shown in FIG. 6. The output voltage is given by
                                                                        V                DAC                            =                            ⁢                                                V                  1                                +                                                                                                    ∑                                                  i                          =                          1                                                                          n                          -                          1                                                                    ⁢                                                                        b                          i                                                ⁢                                                  C                          i                                                                                                                                                              ∑                                                      i                            =                            1                                                                                n                            -                            1                                                                          ⁢                                                  C                          i                                                                    +                                              C                        TERM                                                                              ⁢                                      (                                                                  V                        3                                            -                                              V                        2                                                              )                                                                                                                          =                            ⁢                                                V                  1                                -                                                                                                    ∑                                                  i                          =                          1                                                                          n                          -                          1                                                                    ⁢                                                                        (                                                      1                            -                                                          b                              i                                                                                )                                                ⁢                                                  C                          i                                                                                                                                                              ∑                                                      i                            =                            1                                                                                n                            -                            1                                                                          ⁢                                                  C                          i                                                                    +                                              C                        TERM                                                                              ⁢                                      (                                                                  V                        3                                            -                                              V                        2                                                              )                                                                                                          (        3        )            
when the most significant bit, bn, is 1 or 0 respectively. FIG. 6 illustrates this output.
The dc level of the output voltage is set by V1, while the output range of the DAC is set by the relative size of the switched capacitors and the terminating capacitor (or load, if the DAC is used without a buffer), and the difference between V3 and V2.
In the case of where a pixel of a liquid crystal display is driven with a fixed counter electrode voltage VCOM a wide range of pixel voltages are required, which must be generated by the DAC used to drive the source line SL of FIG. 1. This necessitates either large capacitors (especially if the DAC is used without a buffer, since the DAC capacitors must be large relative to the load—which is itself large), or a high value of (V3−V2). Neither of these is desirable: large capacitors increase the area required for the DAC, whereas a high value of (V3−V2) may make the voltages more difficult to generate.
It would therefore be advantageous to reduce the output range required for the DAC, so allowing relatively small capacitors and relatively low voltages to be used.
FIG. 7 shows a further prior art DAC. This is a “segmented” DAC, of the type disclosed in U.S. Pat. No. 6,154,121. The segmented DAC of FIG. 7 receives a k-bit data input, of which the m most significant bits of the data select the reference voltages to be used by a DAC 11 controlled by the n least significant bits of the input data. For example, the most significant bits of the input data will determine whether the DAC output corresponding to the least significant bits is in the range V1 to V2, V2 to V3, V3 to V4 etc. The resulting output is therefore made up of segments, each of which is continuous with its neighbours.
In the segmented DAC of FIG. 7, the k-bit input data is input to a store 9, and the m most significant bits are passed to a 2m decoder 10a and a reference selector 10b of a first DAC stage 10. The reference selector 10b selects two (or more) voltages from a plurality of reference voltages and provides the selected voltages to the DAC of a second DAC stage 11; these voltages constitute, for example the DAC reference voltages V1, V2 of FIG. 3. The voltages selected by the reference selector 10b are determined by the output from the decoder 10a which, in turn, is determined by the m most significant bits of the input data. That is, the reference voltages supplied to the DAC are controlled by the input data.
Bipolar DACs are required to generate positive and negative output voltages in response to signed digital data (in signed digital data, the most significant bit of the input data represent the sign (positive or negative) of the input data. One method of doing this is described in U.S. Pat. No. 4,853,698, from which FIG. 8 is taken. In the circuit of FIG. 8, the voltage connected to the lower plates of the capacitors is chosen to be either positive or negative, ±Vref, in dependence on the most significant bit of the input data. The most significant bit of the input data controls a switching arrangement 12 to select either +Vref or −Vref depending on the most significant bit of the input data. The two segments of the output extend from −Vref to ground, and from ground to Vref.
In this type of DAC the sign of the reference voltage is determined by the input data.
UK patent publication No. 2414848 describes a system whereby image data is sent to a multiple view directional display with an additional bit. The additional bit indicates whether the image is intended to be visible from the left or right side of the display. Within the display, the additional bit selects a different range of voltages for the DAC, with the voltage range dictating the angle at which the image will be visible. In the DAC of FIG. 9, which is taken from UK patent publication No. 2 414 848, the additional bit OIF selects the DAC reference voltages to be either V1 and V2 or V3 and V4 by means of switches 13-16 and an inverter 17.
In the system of UK patent publication No. 2414848, the connection of the reference voltages is again controlled by the data sent to the display by the host. Moreover, the additional bit OIF selects the DAC reference voltages to be either V1 and V2, or V3 and V4, for every capacitor.
US 2002/0186157 discloses a digital to analogue converter for converting an n-bit digital word. In order to reduce the area of the DAC, it has only m (where m<n) switched capacitors, which receive the m least significant bits of the input n-bit data word.
The remaining (n−m) bits of an input data word are input to a resistive divider circuit, which is connected between first and second reference voltages. The resistive divider circuit generate a voltage whose level depends on the values of the n−m most significant bits of the input data word. In the reset phase, the voltage produced by the resistive divider circuit is supplied to the output terminal of each of the switched competitors of the DAC.